1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device controlled by external control signals.
2. Description of the Prior Art
FIG. 16 illustrates the layout of a conventional dynamic random access memory (hereinafter referred to as DRAM).
Referring to FIG. 16, this DRAM comprises a rectangular semiconductor substrate 100 and memory mats MM1 to MM4 provided on four corners of the semiconductor substrate 100 respectively. Each memory mat MM includes a plurality of (nine in FIG. 16) sense amplifier zones SA1 to SA9 and memory arrays MA1 to MA8 arranged between the sense amplifier zones SA1 to SA9 respectively. A row decoder RD and a column decoder CD are provided in correspondence to each memory mat MM. A column selection line CSL is provided across the sense amplifier zones SA1 to SA9 and the memory arrays MA1 to MA8 of each memory mat MM. An end of the column selection line CSL is connected to the column decoder CD. Word lines WL are provided in each memory array MA to perpendicularly intersect with the column selection line CSL, and first ends of the word lines L are connected to the row decoder RD.
A plurality of input buffers 101 and a control circuit 102 are provided on the region between the memory mats MM1 to MM4. The control circuit 102 generates various internal signals in response to various signals externally supplied through the plurality of input buffers 101, and supplies the internal signals to each row decoder RD and each column decoder CD through signal lines SL1 to SL4.
The signal line SL1 is provided in correspondence to each of a row decoder activation signal RXTM, a row decoder reset signal ZXRSTM, a sense amplifier inactivation signal ZSRSTM and sense amplifier activation signals SONM and SOPM. The signal line SL2 is provided in correspondence to each of predecode signals X0 to X27. The signal line SL3 is provided in correspondence to each of predecode signals Y0 to Y27. The signal line SL4 is provided in correspondence to a column decoder activation signal CDE. While the signal lines SL1, SL2 and SL3 are provided in plural respectively, FIG. 16 shows only single ones thereof for simplifying the illustration.
The control circuit 102 is arranged at the center of the semiconductor substrate 100, for equalizing the wiring lengths between the control circuit 102 and the four row decoders RD1 to RD4 as well as those between the control circuit 102 and the four column decoders CD1 to CD4 with each other.
FIG. 17 is a circuit block diagram showing the structures of the memory array MA1 and the sense amplifier zone SA1 shown in FIG. 16.
Referring to FIG. 17, the memory array MA1 includes a plurality of memory cells MC arranged in rows and columns, word lines WL provided in correspondence to the respective rows, and bit line pairs BL and /BL provided in correspondence to the respective columns. The memory cell MC is well-known one including access transistor and capacitor for storing information. The word line WL transmits an output of the row decoder RD and activates the memory cells MC of selected row. The bit line pair BL and /BL input/output data signal in/from the selected memory cell MC.
The sense amplifier zone SA1 has a pair of data input/output lines IO and /IO, column selector gates 103, sense amplifiers 104 and equalizers 105. Column selector gate 103, sense amplifier 104 and equalizer is provided in correspondence to the respective columns of the memory array MA1.
Each column selector gate 103 includes a pair of N-channel MOS transistors connected between the bit line pair BL and /BL of the corresponding column and the pair of data input/output lines IO and /IO. A gate of the N-channel MOS transistor is connected to the column decoder CD through the column selection line CSL for the corresponding column. When the column decoder CD sets the column selection line CSL high for selection, the N-channel MOS transistors conduct to connect the bit line pair BL and /BL with the data input/output line pair IO and /IO.
The sense amplifier 104 responsively amplifies small potential difference between the bit lines BL and /BL to a power supply voltage Vcc when sense amplifier activation signals SON and ZSOP go high and low respectively. The equalizer 105 responsively equalizes the potentials of the bit lines BL and /BL with a bit line potential VBL when a bit line equalize signal BLEQ goes high for activation.
The row decoder RD generates the control signals SON, ZSOP and BLEQ in accordance with predecode signals X0 to X23 and the control signals RXTM, ZSRSTM and ZXRSTM from the control circuit 102 and sets one of the plurality of word lines WL high for selection. The column decoder CD sets one of the plurality of column selection lines CSL high for selection in accordance with the predecode signals Y0 to Y19 and the control signal CDE from the control circuit 102.
In a write mode, the column decoder CD sets the column selection line CSL for the column responsive to the predecode signals Y0 to Y27 high for activation and makes the column selector gate 103 conduct. Externally supplied write data is supplied to the bit line pair BL and /BL for the selected column through the data input/output line pair IO and /IO. This write data is supplied as the potential difference between the bit lines BL and /BL. Then, the row decoder RD sets the word line WL of the row responsive to the predecode signals X0 to X27 high for selection and activates the memory cells MC of this row. Capacitor of the selected memory cell MC stores charges in a quantity responsive to the potential of the bit line BL or /BL.
In a read mode, the bit line equalize signal BLEQ first falls to a low level for inactivation, and the equalizer 105 is inactivated to stop equalization of the bit lines BL and /BL. The row decoder RD sets the word line WL for the row corresponding to the predecode signals X0 to X27 high for selection. The potentials of the bit lines BL and /BL slightly change in response to the quantity of charges stored in the activated memory cells MC.
Then, the sense amplifier activation signals SON and ZSOP go high and low respectively, for activating the sense amplifier 104. If the potential of the bit line BL is slightly higher than that of the bit line /BL, the former and the latter are pulled up and down to high and low levels respectively. If the potential of the bit line /BL is slightly higher than that of the bit line BL, on the other hand, the former and the latter are pulled up and down to high and low levels respectively.
Then, the column decoder CD sets the column selection line CSL for the column corresponding to the predecode signals Y0 to Y27 high for selection and makes the column selector gate 103 of this column conduct. The data of the bit line pair BL and /BL for the selected column is outputted to the exterior through the column selector gate 103 and the data input/output line pair IO and /IO.
A row selection method of this DRAM is now described in detail. As shown in FIG. 18, the plurality of input buffers 101 are provided in correspondence to external control signals ext./RAS, ext./CAS, ext./WE and ext./CS, external address signals ext.A0 to ext.A12, external bank address signals ext.BA0 and ext.BA1 and an external clock signal ext.CLK respectively.
Each input buffer 101 includes a differential amplifier 115 formed by P-channel MOS transistors 111 and 112 and N-channel MOS transistors 113 and 114 and a buffer 118 formed by two invertors 116 and 117. The differential amplifier 115 compares the level of the corresponding external signal (e.g., ext./RAS) with a reference potential Vref and responsively outputs a low-level signal when the level of the external signal ext./RAS drops below the reference potential Vref. The buffer 118 receives an output signal of the differential amplifier 115 and supplies this signal to the control circuit 102 as an internal signal int./RAS.
FIGS. 19 and 20 are circuit diagrams showing the structures of signal generation circuits 120, 130.1 to 130.4, 142.1, 142.2 and 146.1 to 146.13 included in the control circuit 102.
The signal generation circuit 120 includes a delay circuit 122 formed by odd stages of (five in FIG. 19) invertors 121 and an AND gate 125 formed by a NAND gate 123 and an invertor 124. The internal clock signal int.CLK is inputted in a first input node of the AND gate 125 through the delay circuit 122 and directly inputted in a second input node of the AND gate 125. The AND gate 125 outputs a clock signal CLK. As shown in FIGS. 21B and 21C, the clock signal CLK goes high only for a prescribed time from the leading edge of the internal clock signal int.CLK. The clock signal CLK is supplied to each of the signal generation circuits 130.1 to 130.4, 142.1, 142.2 and 146.1 to 146.13.
The signal generation circuits 130.1 to 130.4 are provided in correspondence to internal control signals int./RAS, int./CAS, int./WE and int./CS respectively. The signal generation circuit 130.1 includes a transfer gate 131, an invertor 132, a latch circuit 136 and a gate circuit 141. The transfer gate 131 has a first conducting electrode receiving the corresponding internal control signal int./RAS, a P-channel MOS transistor side gate receiving the clock signal CLK and an N-channel MOS transistor side gate receiving an inversion signal (output of the invertor 132) of the clock signal CLK. The transfer gate 131 conducts when the clock signal CLK is at a low level and supplies the internal control signal int./RAS to the latch circuit 136. The latch circuit 136, including invertors 133 to 135, latches the signal supplied from a second conducting electrode of the transfer gate 131 and an inversion signal thereof and supplies these signals to the gate circuit 141.
The gate circuit 141 includes NAND gates 137 and 138 and invertors 139 and 140. First input nodes of the NAND gates 137 and 138 receive the clock signal CLK, while second input nodes thereof receive the inversion output signal and the output signal of the latch circuit 136 respectively. Output signals of the NAND gates 137 and 138 are inputted in the invertors 139 and 140 respectively. The invertors 139 and 140 output signals RAS0 and ZRAS0 respectively. As shown in FIGS. 21A to 21G, the gate circuit 141 conducts and the signals RAS0 and ZRAS0 go high and low respectively when the clock signal CLK is at a high level, while the output signals RAS0 and ZRAS0 of the gate circuit 141 are fixed at low levels when the clock signal CLK is at a low level.
The signal generation circuits 130.2 to 130.4 are similar to the signal generation circuit 130.1. The signal generation circuits 130.2 to 130.4 output signals CAS0 and ZCAS0, WE0 and ZWE0, and CS0 and ZCS0 respectively.
The signal generation circuits 142.1 and 142.2 are provided in correspondence to internal bank address signals int.BA0 and int.BA1 respectively. The signal generation circuit 142.1 is different from the signal generation circuit 130.1 only in a point that a flip-flop 145 formed by NAND gates 143 and 144 is newly provided. The flip-flop 145 is set by an output of a NAND gate 137 and reset by that of a NAND gate 138, for outputting signals BAD0 and ZBAD. Invertors 139 and 140 output signals BA0.0 and ZBA0.0 respectively.
The signal generation circuit 142.2 is similar to the signal generation circuit 142.1. This signal generation circuit 142.2 outputs signals BAD1, ZBAD1, BA0.1 and ZBA0.1.
The signal generation circuits 146.1 to 146.13 are provided in correspondence to internal address signals int.A0 to int.A12 respectively. Each of the signal generation circuits 146.1 to 146.13 is different from the signal generation circuit 142.1 in a point that no invertors 139 and 140 are provided. The signal generation circuits 146.1 to 146.13 output signals AD0 and ZAD0, . . . , AD12 and ZAD12 respectively.
The signals RAS0 and ZRAS0, . . . , CAS0 and ZCAS0 generated in the signal generation circuits 130.1 to 130.4 shown in FIG. 19 are supplied to an instruction decoder 150 shown in FIG. 22. The instruction decoder 150 includes four-input NAND gates 151 to 156 provided in correspondence to row activation instruction signals ZACTF and ZPRE, an interruption instruction signal ZTERM, an automatic refresh operation start instruction signal ZAUTOREF, a read burst operation start instruction signal ZREAD and a write burst operation start instruction signal ZWRITE respectively.
When the signals CS0, RAS0, ZCAS0 and ZWE0 go high, the output of the NAND gate 151, i.e., the row activation instruction signal ZACTF goes low for activation. When the signals CS0, RAS0, ZCAS0 and WE0 go high, the output of the NAND gate 152, i.e., the row activation instruction signal ZPRE goes low for activation. When the signals CS0, ZRAS0, ZCAS0 and WE0 go high, the output from the NAND gate 153, i.e., the interruption instruction signal ZTERM for a write/read burst operation goes low for activation.
When the signals CS0, RAS0, CAS0 and ZWE0 go high, the automatic refresh operation start instruction signal ZAUTOREF outputted from the NAND gate 154 goes low for activation. When the signals CS0, ZRAS0, CAS0 and ZWE0 go high, the read burst operation start instruction signal ZREAD outputted from the NAND gate 155 goes low for activation. When the signals CS0, ZRAS0, CAS0 and WE0 go high, the write burst operation start instruction signal ZWRITE outputted from the NAND gate 156 goes low for activation.
FIG. 23 is a circuit diagram showing the structure of a signal generation circuit for generating a row activation signal ZRASE.
Referring to FIG. 23, this signal generation circuit includes a resistive element 157, a capacitor 158, NAND gates 161 to 163, NOR gates 165 to 167 and an invertor 168, and the NAND gates 162 and 163 form a flip-flop 164.
The resistive element 157and the capacitor 158 are connected between lines of a power supply potential Vcc and a ground potential GND. A node N 157 between the resistive element 157 and the capacitor 158 outputs a signal ZPOR for initializing the circuit upon power supply. The signal ZPOR is inputted in a first reset terminal 164a of the flip-flop 164.
The NAND gate 161 receives the signals BA0.0 and BA0.1. The NOR gate 165 receives an output of the NAND gate 161 and the signal ZACTF. The NOR gate 166 receives a signal ACTS and an output of the NOR gate 165, while an output thereof is inputted in a set terminal 164c of the flip-flop 164. The NOR gate 167 receives the output of the NAND gate 161 and a signal ZPREC, while an output thereof is inputted in a second reset terminal 164b of the flip-flop 164 through the invertor 168. An inversion output of the flip-flop 164 forms the row activation signal ZRASE.
FIG. 24 is a circuit diagram showing the structure of a signal generation circuit for generating various control signals in response to the row activation signal ZRASE.
Referring to FIG. 24, this signal generation circuit includes NAND gates 171 to 173, a NOR gate 174, delay circuits 175 to 179 and invertors 180 to 185. The row activation signal ZRASE is directly inputted in first input nodes of the NAND gates 171 and 172 and inputted in a second input node of the NAND gate 172 through the delay circuit 175 formed by two invertors. An output of the NAND gate 172 is delayed by the invertors 181 and 182, to form the row decoder reset signal ZXRSTM.
The output of the NAND gate 172 is directly inputted in a first input node of the NOR gate 174 and inputted in a second input node of the NOR gate 174 through the invertor 181 and the delay circuit 177 formed by five invertors. An output of the NOR gate 174 is inverted by the invertor 183, to form the sense amplifier inactivation signal ZSRSTM.
The signal ZSRSTM is inputted in a second input node of the NAND gate 171 through the invertor 180. An output of the NAND gate 171 forms a row address buffer activation signal RADE. The signal RADE is delayed by the delay circuit 176 formed by two invertors, to form a signal RADED.
The signal ZSRSTM is delayed by the delay circuit 178 formed by four invertors, to form the sense amplifier activation signal SONM. The signal ZSRSTM is further inputted in a first input node of the NAND gate 173 through the delay circuit 179 formed by four invertors. The row activation signal ZRASE is inputted in a second input node of the NAND gate 173 through the invertor 184. An output of the NAND gate 173 is inverted by the invertor 185, to form the row decoder activation signal RXTM.
FIGS. 25A to 25M are timing charts showing operations of the circuits shown in FIGS. 22 to 24.
Referring to FIGS. 25A to 25M, a row access instruction (ACT instruction) has prescribed set-up and holding times, and is applied in synchronization with the leading edge of the external clock signal ext.CLK. At this time, the automatic refresh activation signal ACTS is at a low level, while the signals ZPREC and ZPOR are at high levels. The ACT instruction is issued by setting the external control signals ext./CS, ext./RAS, ext./CAS and ext./WE low, low, high and high respectively.
When the ACT instruction is issued and both of the external bank address signals ext.BA0 and ext.BA1 specifying a bank for vow access go low, the signals ZACTF, BA0.0 and BA0.1 go low, high and high respectively while the clock signal CLK is at a high level. Thus, the flip-flop 164 is set and the signal ZRAS falls to a low level for activation, and the signals RADE, RADED, ZXRSTM, ZSRTSM, SONM and RXTM go high in response.
A row access end instruction (PRE instruction) is issued by setting the external control signals ext./CS, ext./RAS, ext./CAS and ext./WE low, low, high and low respectively. At this time, the signals ACTS, ZACTF and ZPOR are at low, high and high levels respectively.
When the PRE instruction is issued and the external bank address signals ext.BA0 and ext.BA1 go low, the signals PREC, BA0.0 and BA0.1 go low, high and high respectively while the clock signal CLK maintains the high level. Thus, the flip-flop 164 is reset and the signal ZRASE goes high for inactivation, so that the signals RADE, RADED, ZXRSTM, ZSRSTM, SONM and RXTM go low in response.
FIG. 26 is a circuit diagram showing the structure of a signal generation circuit for decoding the signals SONM, SOPM, ZSRSTM and ZXRSTM by a block decode signal Xn (n: integer of 20 to 27) and generating the signals BLEQ, SON, ZSOP and ZXRST.
This signal generation circuit is provided in correspondence to each sense amplifier zone SA. The signal SOPM is obtained by delaying the signal SONM (see FIG. 2). Referring to FIG. 26, the signal generation circuit includes NAND gates 190 to 193, NOR gates 194 and 195, invertors 196 to 200, P-channel MOS transistors 201 and 202 and N-channel MOS transistors 203 to 205.
When both of the signals Xn and ZSRSTM go high, an output of an AND gate formed by the NAND gate 190 and the invertor 196, i.e., the bit line equalize signal BLEQ goes high.
When one of the signal Xn and a signal Xn+1 goes high and the signal ZSRSTM goes high, outputs of the invertor 197 and the NOR gate 194 go low, while that of the NOR gate 195 goes high. At this time, the NAND gates 191 and 192 operate as invertors for the signals SONM and SOPM respectively. The signal SONM is delayed by the NAND gate 191 and the invertor 198, to form the signal SON. The signal SOPM is delayed by the NAND gate 192 and the invertors 199 and 200, to form the signal ZSOP.
When the signals Xn and ZXRSTM go high, the N-channel MOS transistors 203 and 204 conduct, the NAND gate 193 outputs a low level and the N-channel MOS transistor 205 enters a non-conducting state. Thus, the P-channel MOS transistors 201 and 202 enter non-conducting and conducting states respectively, and the signal ZXRST goes high. When at least one of the signals Xn and ZXRSTM goes low, the signal ZXRST goes low.
FIG. 27 is a circuit diagram showing the structure of a switching circuit for switching an address signal (e.g., AD0) generated in accordance with an external address signal and a refresh address signal (e.g., Q0) generated in the interior of the DRAM chip.
Referring to FIG. 27, the switching circuit includes clocked invertors 211 and 212 and invertors 213 to 217, and the invertors 216 and 217 form a latch circuit 218. The signal ZACTF is inverted by the invertor 213, to form a signal ZRAL for incorporating the external address signal. A signal ZQAL for incorporating the refresh address signal Q0 goes high when the automatic refresh signal ZAUTOREF goes low.
When the signals ZRAL and ZQAL go high and low respectively, the clocked invertor 211 is activated and the address signal AD0 is latched by the latch circuit 218, to form a signal RA0. When the signals ZRAL and ZQAL go low and high respectively, on the other hand, the docked invertor 212 is activated and the address signal Q0 is latched by the latched circuit 218, to form the signal RA0.
FIG. 28 is a circuit diagram showing the structure of an address buffer. Referring to FIG. 28, this address buffer includes a transfer gate 221, invertors 222 to 226, NAND gates 227 to 229 and a NOR gate 230.
When a burn-in test signal WBI is at a low level for inactivation, each of the NAND gate 227 and the NOR gate 230 operates as an invertor for an input. The transfer gate 221 conducts so that the address signal RA0 is incorporated in a node N221 while the signal RADED is at a low level. A latch circuit formed by the invertor 223 and the NOR gate 230 latches the level of the node N221.
While the signal RADE is at a high level, the NAND gates 228 and 229 operate as invertors for inputs. The address signal RA0 incorporated in the node N221 is delayed by the NAND gate 228 and the invertor 225, to form an address signal RAD0. The address signal RA0 incorporated in the node N221 is further delayed by the NAND gates 227 and 229 and the invertor 226, to form an address signal ZRAD0. When the burn-in test signal WBI is at a high level for activation, the node N221 is fixed at a high level and the address signals RAD0 and ZRAD0 can be generated with no input of the address signal RA0.
FIGS. 29A to 29E are circuit diagrams showing the structure of a predecoder. Referring to FIGS. 29A to 29E, this predecoder includes AND gates 231 to 235 formed by NAND gates and invertors. The AND gate 231 is provided in correspondence to each of the signals X0 to X3. Two of the signals ZRAD0, RAD0, ZRAD1 and RAD 1 are previously assigned to each AND gate 231. Each AND gate 231 responsively sets the corresponding signal X high when the previously assigned signals go high.
Similarly, signals X4 to X11 are generated from signals ZRAD2, RAD2 to ZRAD4 and RAD4. Signals X12 to X15 are generated from signals ZRAD5, RAD5, ZRAD6 and RAD6. Signals X16 to X19 are generated from signals ZRAD7, RAD7, ZRAD8 and RAD8. Signals X20 to X27 are generated from signals ZRAD9, RAD9 to ZRAD11 and RAD11.
FIG. 30 is a circuit diagram showing the structure of a signal generation circuit for decoding the signals X0 to X19 with block signals X20 to X27 and generating local signals XD0 to XD19.
Referring to FIG. 30, this signal generation circuit includes NAND gates 241 and 242 and invertors 243 and 244. The signal generation circuit is provided in correspondence to each block. When the signal X (e.g., X20) for selecting the corresponding block as well as the row decoder activation signal RXTM also go high, each of the NAND gates 241 and 242 operates as an invertor for input signals.
The NAND gate 241 and the invertor 243 are provided in correspondence to each of the signals X0 to X3. The NAND gate 242 and the invertor 244 are provided in correspondence to each of the signals X4 to X19. Each of the signals X0 to X3 is delayed by the corresponding NAND gate 241 and the corresponding invertor 243, to form each of signals XD0 to XD3. Each of the signals X4 to X19 is delayed by the corresponding NAND gate 242 and the corresponding invertor 244, to form each of signals XD4 to XD19.
FIG. 31 is a circuit diagram showing the structure of a word line drive circuit for selecting each word line WL in response to the address signals XD0 to XD19.
Referring to FIG. 31, this word line drive circuit includes a NAND gate 251, an N-channel MOS transistor 258, P-channel MOS transistors 259 and 260 and an invertor 261.
The NAND gate 251 includes P-channel MOS transistors 252 to 254 connected in parallel between lines of the power supply potential Vcc and an output node 251a and N-channel MOS transistors 255 to 257 serially connected between the output node 251a and a line of the ground potential GND. Gates of the MOS transistors 252 and 257 are connected in common for receiving a signal (e.g., XD16) previously assigned to the corresponding word line WL among the address signals XD16 to XD19. Gates of the MOS transistors 253 and 256 are connected in common for receiving a signal (e.g., XD12) previously assigned to the corresponding word line WL among the address signals XD12 to XD15. Gates of the MOS transistors 254 and 255 are connected in common for receiving a signal (e.g., XD4) previously assigned to the corresponding word line WL among the address signals XD12 to XD15.
When the previously assigned signals XD16, XD12 and XD4 go high, the P-channel MOS transistors 252 to 254 and the N-channel MOS transistors 255 to 257 enter non-conducting and conducting states respectively, and the output node 251a goes low.
The N-channel MOS transistor 258 is connected between the output node 251a of the NAND gate 251 and an input node 261a of the invertor 261 for receiving a signal (e.g., XD0) previously assigned to the corresponding word line WL among the address signals XD0 to XD3 in the gate thereof. When the previously assigned signal XD0 goes high, the N-channel MOS transistor 258 conducts to connect the output node 251a of the NAND gate 251 with the input node 261a of the invertor 261.
The P-channel MOS transistor 259 is connected between a line of the power supply potential Vcc and the input node 261a of the invertor 261, for receiving the row decoder reset signal ZXRST in the gate thereof. When the signal ZXRST goes low for activation, the P-channel MOS transistor 259 conducts to reset the node 261a at a high level.
The P-channel MOS transistor 260 is connected between a line of a step-up potential Vpp and the input node 261a of the invertor 261, and has a gate connected to an output node 261b of the invertor 261. When the input and output nodes 261a and 261b of the invertor 261 go high and low respectively, the P-channel MOS transistor 260 conducts and the input node 261a is latched at the high level. However, the gate width of the P-channel MOS transistor 260 is set smaller than those of the N-channel MOS transistors 255 to 258, and hence the input node 261a goes low when the N-channel MOS transistors 255 to 258 conduct.
The invertor 261 includes a P-channel MOS transistor 262 which is connected between a line of the power supply potential Vcc and the output node 261b and has a gate connected to the input node 261a and an N-channel MOS transistor 263 which is connected between the output node 261b and a line of the ground potential GND and has a gate connected to the input node 261a. The output node 261b of the invertor 261 is connected to the corresponding word line WL. When the input node 261a goes low, the P-channel and N-channel MOS transistors 262 and 263 enter conducting and non-conducting states respectively and the corresponding word line WL goes high for selection. Thus, an N-channel MOS transistor Q included in each memory cell MC connected to the word line WL conducts and a capacitor C included in the memory cell MC is connected with the bit line BL or /BL, to enable data reading/writing.
In the conventional DRAM having the aforementioned structure, the chip area increases following increase of the storage capacity of the DRAM, the lengths of signal lines increase and the operating speed-is retarded when the number of signals increases.